Modules
Uses Rust’s cpuid function from the arch module.
Macros
Macro which queries cpuid directly.
Structs
Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).
Used to iterate over cache information contained in cpuid instruction.
Main type used to query for information about the CPU we’re running on.
Low-level data-structure to store result of cpuid instruction.
Deterministic Address Translation Structure
Deterministic Address Translation Structure Iterator
EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section
Iterates over the system topology in order to retrieve more system information at each level of the topology.
Gives detailed information about the current level in the topology (how many cores, what type etc.).
Information about Hypervisor (https://lwn.net/Articles/301888/)
L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 2).
L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 1).
Memory Bandwidth Allocation Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 3).
Processor Frequency Information
Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0 and ECX = 1)
Iterator over the SGX sub-leafs (ECX >= 2).
Time Stamp Counter and Nominal Core Crystal Clock Information Leaf.
Enums
What type of cache are we dealing with?
Deterministic Address Translation cache type (EDX bits 04 – 00)
Identifies the different Hypervisor products.
Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
What type of core we have at this level in the topology (real CPU or hyper-threaded).
Constants
This table is taken from Intel manual (Section CPUID instruction).